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DATA SHEET
MOS INTEGRATED CIRCUIT
PD77016
16 bits, Fixed-point Digital Signal Processor
PD77016 is a 16 bits fixed-point DSP (Digital Signal Processor) developed for digital signal processing with its
demand for high speed and precision.
FEATURES * FUNCTIONS
* Instruction cycle: 30 ns (MIN.) with 33 MHz clock * Dual load/store * Hardware loop function * Conditional execution * Executes product-sum operation in one instruction cycle
* PROGRAMMING
* 16 bits x 16 bits + 40 bits 40 bits multiply accumulator * 8 general registers (40 bits each) * 8 ROM/RAM data pointer: each data memory area has 4 registers * 10 source interrupts (external: 4, internal: 6) * 3 operand instructions (example: R0 = R0 +R1LR2L) * Nonpipeline on execution stage
* MEMORY AREAS
* Program memory area: 64K words x 32 bits * Two independent data memory areas: 64K words x 16 bits (X/Y memory)
* ON-CHIP PERIPHERAL
* I/O port: 4 bits * Serial I/O (16 bits): 2 channels
* CMOS * +5 V single power supply ORDERING INFORMATION
Part Number Package
PD77016GM-KMD 160-pin plastic QFP (FINE PITCH) (24 x 24 mm)
The information in this document is subject to change without notice. Document No. U10891EJ5V0DS00 (5th edition) Date Published April 1998 N CP(K) Printed in Japan
The mark
shows major revised points.
(c)
1992, 1994, 1995
2
X-Bus External Memory Y-Bus Serial I/O #1 X Memory Data Pointers X Memory 2KW-RAM Y Memory Data Pointers Y Memory 2KW-RAM R0-R7 Serial I/O #2 Main Bus ALU (40) Ports Loop Control Stack Instruction Memory (1.5 KW-RAM) MPY 16 x 16 + 40 40 Interrupt Control Host I/O CPU Control PC Stack Wait Controller INT1-INT4 WAIT RESET CLKOUT CLKIN External Instruction Memory IE I/O
BLOCK DIAGRAM
PD77016
PD77016
FUNCTIONAL PIN GROUPS
+5 V
Serial Interface #1

(4)
SO1 SORQ1 SOEN1 SCK1 SI1 SIEN1 SIAK1 SO2 SORQ2 SOEN2 SCK2 SI2 SIEN2 SIAK2
VDD
RESET INT1 INT2 INT3 INT4 CLKIN CLKOUT PWR TDO,TICE TCK,TDI,TMS IA0 - IA15 ID0 - ID31 HOLDRQ (2) (3) (16) (32)

Interrupts
Serial Interface #2

Debugging Interface External Instruction Memory
Ports
P0 - P3
BSTB HOLDAK

Data Bus Control
Host Interface

HCS (2) HA0,HA1 HRD HRE HWR HWE (8) HD0 - HD7 GND
X/Y DA0 - DA15 D0 - D15 WAIT MRD MWR (16) (16) External Data Memory
3
4
Functional Differences among the PD7701x Family
Item Internal instruction RAM Internal instruction ROM External instruction memory Data RAM (X/Y memory) Data ROM (X/Y memory) External data memory Instruction cycle (Maximum operation speed) External clock (at maximum operation speed) Crystal (at maximum operation speed) Instruction Serial interface (2 Channels)
PD77016
1.5K words None 48K words 2K words each None 48K words each
PD77015
PD77017
PD77018
256 words
PD77018A
PD77019
PD77019-013
4K words
4K words
12K words None
24K words
None
1K words each 2K words each
2K words each 4K words each
3K words each 12K words each 16K words each None
30 ns (33 MHz) 33/16.5/8.25/4.125 MHz Variable multiple rate (1, 2, 4, 8 ) by mask option.
16.6 ns (60 MHz) 60/30/20/15/7.5 MHz Variable multiple rate (1, 2, 3, 4, 8 ) by mask option. 60 MHz STOP instruction is added. 15 MHz Multiple rate is fixed to 4. -
66 MHz
- - Channel 1 has the same functions as channel 2. 5V 160-pin plastic QFP
33 MHz
Channel 1 has the same functions as that of the PD77016. Channel 2 has no SORQ2 or SIAK2 pin (Channel 2 is used for CODEC connection). 3V 100-pin plastic TQFP 100-pin plastic TQFP 116-pin plastic BGA 100-pin plastic TQFP
Power supply Package
Remark
The PD77019-013 internal ROM area is masked already by the void code to use as RAM based DSP without mask code ordering process.
PD77016
PD77016
PIN CONFIGURATION
PD77016GM-KMD
160-pin plastic QFP (FINE PITCH) (24 x 24 mm) (Top View)
160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 RESET INT4 INT3 INT2 INT1 WAIT HOLDRQ CLKIN P3 P2 P1 P0 CLKOUT GND VDD MWR MRD BSTB HOLDAK X/Y DA15 DA14 DA13 DA12 GND VDD DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 GND VDD DA3 DA2 DA1 DA0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 IA0 IA1 IA2 IA3 VDD GND IA4 IA5 IA6 IA7 IA8 IA9 IA10 IA11 VDD GND IA12 IA13 IA14 IA15 TMS TDI TCK TIC TDO VDD GND HWE HRE HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HA1 HA0 HWR
D15 D14 D13 D12 GND VDD D11 D10 D9 D8 D7 D6 D5 D4 GND VDD D3 D2 D1 D0 GND VDD SI1 SIEN1 SCK1 SIAK1 SO1 SORQ1 SOEN1 GND VDD SOEN2 SORQ2 SO2 SIAK2 SCK2 SIEN2 SI2 HCS HRD
NC ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 VDD GND ID8 ID9 ID10 ID11 ID12 ID13 ID14 ID15 VDD GND ID16 ID17 ID18 ID19 ID20 ID21 ID22 ID23 VDD GND PWR ID24 ID25 ID26 ID27 ID28 ID29 ID30 ID31
5
PD77016
PIN IDENTIFICATION
BSTB: CLKIN: CLKOUT: D0-D15: DA0-DA15: GND: HA0,HA1: HCS: HD0-HD7: HOLDAK: HOLDRQ: HRD: HRE: HWE: HWR: IA0-IA15: ID0-ID31: INT1-INT4: MRD: MWR: N.C: P0-P3: PWR: RESET: SCK1,SCK2: SI1,SI2: SIAK1,SIAK2: SIEN1,SIEN2: SO1,SO2:
Bus Strobe Clock Input Clock Output 16 Bits Data Bus External Data Memory Address Bus Ground Host Data Access Host Chip Select Host Data Bus Hold Acknowledge Hold Request Host Read Host Read Enable Host Write Enable Host Write Instruction Memory Address Output Instruction Data Input Interrupt Memory Read Output Memory Write Output No Connection Port Program Memory Write Strobe Reset Serial Clock Input Serial Data Input Serial Input Acknowledge Serial Input Enable Serial Data Output
SOEN1,SOEN2: Serial Output Enable SORQ1,SORQ2: Serial Output Request TCK: TDI: TDO: TICE: TMS: VDD: WAIT: X/Y: Test Clock Input Test Data Input Test Data Output Test In-Circuit Emulator Test Mode Select Power Supply Wait Input X/Y Memory Select
6
PD77016
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Symbol RESET INT4 INT3 INT2 INT1 WAIT HOLDRQ CLKIN P3 P2 P1 P0 CLKOUT GND VDD MWR MRD BSTB HOLDAK X/Y DA15 DA14 DA13 DA12 GND VDD DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 GND VDD DA3 DA2 DA1 DA0 Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Symbol D15 D14 D13 D12 GND VDD D11 D10 D9 D8 D7 D6 D5 D4 GND VDD D3 D2 D1 D0 GND VDD SI1 SIEN1 SCK1 SIAK1 SO1 SORQ1 SOEN1 GND VDD SOEN2 SORQ2 SO2 SIAK2 SCK2 SIEN2 SI2 HCS HRD Pin No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Symbol HWR HA0 HA1 HD7 HD6 HD5 HD4 HD3 HD2 HD1 HD0 HRE HWE GND VDD TDO TICE TCK TDI TMS IA15 IA14 IA13 IA12 GND VDD IA11 IA10 IA9 IA8 IA7 IA6 IA5 IA4 GND VDD IA3 IA2 IA1 IA0 Pin No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Symbol ID31 ID30 ID29 ID28 ID27 ID26 ID25 ID24 PWR GND VDD ID23 ID22 ID21 ID20 ID19 ID18 ID17 ID16 GND VDD ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 GND VDD ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 NC
7
PD77016
CONTENTS 1. PIN FUNCTIONS ...............................................................................................................................
1.1 1.2 Pin Functions ...........................................................................................................................................
9
9
Recommended Connection for Unused Pins ....................................................................................... 14
2. FUNCTIONS ...................................................................................................................................... 15
2.1 Pipeline Processing ................................................................................................................................ 15 2.1.1 2.1.2 2.2 2.3 Outline ........................................................................................................................................... 15 Instructions with Delay .................................................................................................................. 15
Program Control Unit .............................................................................................................................. 16 Operation Unit ......................................................................................................................................... 16 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 General register (R0 to R7) ........................................................................................................... 16 MAC: Multiply ACcumulator ......................................................................................................... 17 ALU: Arithmetic Logic Unit ........................................................................................................... 17 BSFT: Barrel ShiFTer ................................................................................................................... 17 SAC: Shifter And Count Circuit .................................................................................................... 17 CJC: Condition Judge Circuit ....................................................................................................... 17 Instruction RAM Outline ................................................................................................................ 19 Data Memory Outline .................................................................................................................... 19 Data Memory Addressing .............................................................................................................. 19 Serial Interface Outline .................................................................................................................. 20 Host Interface Outline .................................................................................................................... 20 General Input/output Ports Outline ................................................................................................ 20 Wait Cycle Register ....................................................................................................................... 20
2.4
Memory ..................................................................................................................................................... 18 2.4.1 2.4.2 2.4.3
2.5
On-chip Peripheral Circuit ...................................................................................................................... 20 2.5.1 2.5.2 2.5.3 2.5.4
3. INSTRUCTIONS ................................................................................................................................ 21
3.1 3.2 Outline ...................................................................................................................................................... 21 Instruction Set and Operation ................................................................................................................ 22
4. ELECTRICAL SPECIFICATIONS ..................................................................................................... 29 5. PACKAGE DRAWING ...................................................................................................................... 50 6. RECOMMENDED SOLDERING CONDITIONS ................................................................................ 51
8
PD77016
1. PIN FUNCTIONS
1.1 Pin Functions * Power supply
Symbol VDD Pin No. 15, 26, 36, 46, 56, 62, 71, 95, 106, 116, 131, 141, 151 14, 25, 35, 45, 55, 61, 70, 94, 105, 115, 130, 140, 150 I/O - +5V power supply Function
GND
-
Ground
* System control
Symbol CLKIN CLKOUT RESET 8 13 1 Pin No. I/O I O I External clock input Internal system clock output Internal system reset signal input Function
* Interrupt
Symbol INT4 - INT1 2, 3, 4, 5 Pin No. I/O I Function Maskable external interrupt input * Falling edge detection
9
PD77016
* External data memory interface
Symbol X/Y 20 Pin No. I/O O (3S) Function Memory select signal output * 0: X memory is used. * 1: Y memory is used. Address bus to external data memory * External data memory is accessed. * During the external memory is not accessed, these pins keep the previous level. These pins are set to low level; 0x0000, by reset. They continue outputting low level until the first external memory access. 16 bits data bus to external data memory * External data memory is accessed. Read output * Reads external memory Write output * Writes external memory Wait signal input * Wait cycle is input when external memory is read. 1: No wait 0: Wait Hold request signal input * Input low level when external data memory bus is expected to use. Bus strobe signal output * Outputs low level while the PD77016 is occupying external memory bus. Hold acknowledge signal output * Outputs low level when the PD77016 permits external device to use external data memory bus.
DA15 - DA0
Note 1.
O (3S)
D15 - D0
Note 2.
I/O (3S) O (3S) O (3S) I
MRD
17
MWR
16
WAIT
6
HOLDRQ
7
I
BSTB
18
O
HOLDAK
19
O
Note 1. 2. Remark
DA15 to DA0 pins are located on Pin No. 21 - 24, 27 - 34, 37 - 40. D15 to D0 pins are located on Pin No. 41 - 44, 47 - 54, 57 - 60. The state of the pins added 3S becomes high impedance when the external memory is not accessed or bus release signal (HOLDAK = 0) is output.
10
PD77016
* Serial interface
Symbol SCK1 SORQ1 SOEN1 SO1 SIEN1 SI1 SCK2 SORQ2 SOEN2 SO2 SIEN2 SI2 SIAK1 SIAK2 65 68 69 67 64 63 76 73 72 74 77 78 66 75 Pin No. I/O I O I O (3S) I I I O I O (3S) I I O O Clock input for serial 1 Serial output 1 request Serial output 1 enable Serial data output 1 Serial input 1 enable Serial data input 1 Clock input for serial 2 Serial output 2 request Serial output 2 enable Serial data output 2 Serial input 2 enable Serial data input 2 Serial input 1 acknowledge Serial input 2 acknowledge Function
Remark
The state of the pins added 3S becomes high impedance, when data output have been finished or RESET is input.
11
PD77016
* Host interface
Symbol HA1 83 Pin No. I/O I Function Specifies register which HD7 to HD0 access 1: Accesses HST: Host interface status register when HA1 = 0 0: Accesses HDT(out): Host transmit data register when HRD = 0 0: Accesses HDT(in): Host receive data register when HWR = 0 Specifies bits of registers which HD7 to HD0 access * 1: Accesses bits 15-8 of HST, HDT (out), HDT (in) * 0: Accesses bits 7-0 of HST, HDT (out), HDT (in) Chip select input Host read input Host write input Host read enable output Host write enable output 8 bits host data bus
HA0
82
I
HCS HRD HWR HRE HWE HD7 - HD0 Remark
79 80 81 92 93 84 - 91
I I I O O I/O (3S)
The state of the pins added 3S becomes high impedance when the host does not access host interface.
* I/O port
Symbol P3 - P0 9 - 12 Pin No. I/O I/O I/O port Function
12
PD77016
* External instructions memory interface
Symbol IA15 - IA0 Note 1. Pin No. I/O O (3S) Function Address bus to external instruction memory * Even the internal instruction memory is accessed, the address is output to the external instruction memory. In this case, the PD77016 ignores data of external instruction memory output. 32 bits instruction input Program memory write strobe * Write strobe for external instruction memory. This pin loads program to external instruction memory (not internal memory) while PD77016 is in boot operation.
ID31 - ID0 PWR
Note 2. 129
I/O (3S) O (3S)
Note 1. 2. Remark
IA15 to IA0 pins are located on these pins: 101 to 104, 107 to 114, 117 to 120 ID31 to ID0 pins are located on these pins: 121 to 128, 132 to 139, 142 to 149, 152 to 159 The state of the pins added 3S becomes high impedance when RESET is input.
* Debugging interface
Symbol TDO TICE TCK TDI TMS 96 97 98 99 100 Pin No. I/O O O I I I For debugging For debugging For debugging For debugging For debugging Function
13
PD77016
1.2 Recommended Connection for Unused Pins
Pin INT1 - INT4 X/Y DA0 - DA15 D0 - D15
Note 1
I/O I O O I/O O I I O O I I I I O O O I I I O
Note 2
Recommended connection connect to VDD open
connect to VDD or GND, via a resistor open connect to VDD
MRD, MWR WAIT HOLDRQ BSTB HOLDAK SCK1, SCK2 SI1, SI2 SOEN1, SOEN2 SIEN1, SIEN2 SORQ1, SORQ2 SO1, SO2 SIAK1, SIAK2 HA0, HA1 HCS HRD, HWR HRE, HWE HD0 - HD7 P0 - P3 ID0 - ID31 IA0 - IA15 PWR TCK TDO, TICE TMS, TDI CLKOUT
open
connect to VDD or GND
connect to GND
open
connect to VDD or GND connect to VDD
open connect to VDD or GND, via a resistor
I/O I/O I/O O O I O I O
open
connect to GND, via a resistor open open(pull-up internally) open
Notes 1. Can leave open, if no access to external data memory is executed in the whole of program. But in the HALT mode when the current consumption is reduced, connect a pin as recommended connection. 2. Can leave open, if HCS, HRD, HWR are fixed to high level. But in the HALT mode when the current consumption is reduced, connect a pin as recommended connection. Remark I: Input pin, O: Output pin, I/O: Input/Output pin
14
PD77016
2. FUNCTIONS
2.1 Pipeline Processing This section describes the PD77016 pipeline processing. 2.1.1 Outline The PD77016 basic operations are executed in following 3-stage pipeline. (1) instruction fetch; if (2) Instruction decoding; id (3) execution; ex When the PD77016 operates a result of a instruction just executed before, the data is input to ALU in parallel with written back to general registers. Pipeline processing actualizes programming without delay time to execute instructions and write back data. Three successive instructions and their processing timing are shown below. Pipeline Processing Timing
if1
id1
ex1
if2
id2
ex2
if3
id3
ex3
1 instruction cycle
2.1.2 Instructions with Delay The following instructions have delay time in execution. (1) Instructions to control interrupt 2 instruction cycles have been taken between instruction fetch and execution. (2) Inter-register transfer instructions and immediate data set instructions When data is set in data pointer, it needs 2 instruction cycles before the data is valid.
15
PD77016
2.2 Program Control Unit Program control unit controls not only count up of program counter in normal operation, but loop, repeat, branch, halt and interrupt. In addition to loop stack of loop 4 level and program stack of 15 level, software stack can be used for multiloop and multi-interrupt/subroutine call. The PD77016 has external 4 interruptions and internal 6 interruptions from peripheral, and specifies interrupt enable or disable independently. The HALT instruction causes the PD77016 to place in low power standby mode. When the HALT instruction is executed, power consumption decreases. HALT mode is released by interrupt input or hardware reset input. It takes several system clock to recover. 2.3 Operation Unit Operation unit consists of the following five parts. - 40 bits general register x 8 for data load/store and input/output of operation data - 16 bits x 16 bits + 40 bits 40 bits multiply accumulator - 40 bits Data ALU - 40 bits barrel shifter - SAC: shifter and count circuit. Standard word length is 40 bits to make overflow check and adjustment easy, and to accumulate the result of 16 bits x 16 bits multiplication correctly.
39 32 31 10 0
SSSSSSSS
Head room
Result of multiplication among two's complement data
2.3.1 General register (R0 to R7) The PD77016 has eight 40 bits registers for operation input/output and load/store with memory. General register consists of the following three parts. - R0L to R7L (bit 15 to bit 0) - R0H to R7H (bit 31 to bit 16) - R0E to R7E (bit 39 to bit 32) But each of RnL, RnH and RnE are treated as a register in the following conditions. (1) General register used as 40 bits register General registers are treated as 40 bits register, when they are used for the following aims. (a) Operand for triminal operation (except for multiplier input) (b) Operand for dyadic operation (except for multiplier and shift value) (c) Operand for monadic operation (except for exponent instructions) (d) Operand for operation (e) Operand for conditional judge (f) Destination for load instruction (with sign extension and 0 clear)
(2) General register used as 32 bits register Bit 31 to bit 0 of general register are treated as 32 bits register, when it is used for a operand of exponent instruction.
16
PD77016
(3) General register used as 24 bits register Bit 39 to bit 16 of general register are treated as 24 bits register, when it is used for destination with extended sign for a load/store instruction. (4) General register used as 16 bits register Bit 31 to bit 16 of general register are treated as 16 bits register, when it is used for the following aims. (a) Signed operand for multiplier (b) Source/destination for load/store instruction Bit 15 to bit 0 of general register are treated as 16 bits register, when it is used for the following aims. (c) Unsigned operand for multiplier (d) Shift value for shift instruction (e) Source/destination for load/store instruction (f) (f) Source/destination for inter-register transfer instruction Hardware loop times (g) Destination for immediate data set instruction
(5) General register used as 8 bits register Bit 39 to bit 32 of general register are treated as 8 bits register, when it is used for source/destination of load/ store instruction. 2.3.2 MAC: Multiply ACcumulator MAC multiplies a pair of 16 bits data, and adds or subtract the result and 40 bits data. MAC outputs 40 bits data. MAC operates three types of multiplication: signed data x signed data, signed data x unsigned data and unsigned data x unsigned data. Result of multiplication and 40 bits data for addition can be added after 1 or 16 bits arithmetic shift right. 2.3.3 ALU: Arithmetic Logic Unit ALU performs arithmetic operation and logic operation. Both input/output data are 40 bits. 2.3.4 BSFT: Barrel ShiFTer BSFT performs shift right/left operation. Both input/output data are 40 bits. There are two types of shift right operations; arithmetic shift right which sign is extended, and logic shift right which is input 0 in MSB first. 2.3.5 SAC: Shifter And Count Circuit SAC calculates and outputs shift value for normalization. SAC is input 32 bits data and outputs the 40 bits data. Then, bit 39 to bit 5 of output data is always 0. 2.3.6 CJC: Condition Judge Circuit CJC judges whether condition is true or false with 40 bits input data. A conditional instruction is executed when the result is true, and not executed when the result is false.
17
PD77016
2.4 Memory The PD77016 has one instruction memory area (64K words x 32 bits) and two data memory areas (64K words x 16 bits each). It adopts Harvard-type architecture, with instruction memory area and data memory areas separated. The PD77016 has 2 sets of data addressing units, which are dedicated for addressing data memory area. Each addressing unit consists of four data pointers, four index registers, a modulo register and addressing ALU. Memory areas are shown below. X memory area addresses are specified by DP0 to DP3, and Y memory area addresses are specified by DP4 to DP7. After memory access, DPn (with the same subscript), can be modified by DNn value. Modulo operation is performed with DMX for DP0 to DP3, with DMY for DP4 to DP7.
Data Memory Area (X/Y Memory) 0xFFFF 0xFFFF
Instruction Memory Area
External Data Memory (48 K words)
External Instruction Memory (48 K words)
0x4000 0x3FFF System 0x3840 0x383F 0x3800 0x37FF
0x4000 0x3FFF
System Peripheral (64 words) 0x0800 0x07FF Internal Instruction RAM (1.5 K words) System 0x0240 0x023F 0x0200 0x01FF Data RAM (2 K words) 0x0100 0x00FF 0x0000 Vector (64 words) System Bootup ROM (256 words)
0x0800 0x07FF
0x0000
Caution
When any data is accessed or stored to system address, normal operation of the PD77016 is not assured.
18
PD77016
2.4.1 Instruction RAM Outline The PD77016 has an instruction RAM (1.5 words x 32 bits). A system vector area is assigned to 64 words of the instruction RAM. Internal RAM is initialized and rewritten by boot program. Additionally external memory expansion is available as the PD77016 has interface with the external instruction memory. When RAM is used as the external memory, it can be initialized and rewritten by boot program. Boot up ROM contains the program loading instruction code to internal and external instruction RAM. When the external instruction memory area is accessed, instruction cycle can be 2 or more by wait function. 2.4.2 Data Memory Outline The PD77016 has two data memory areas (64 words x 16 bits each) in X and Y memory areas. Each memory areas consists of 2K words x 16 bits data RAM. Additionally, data memory expansion is available as the PD77016 has interface with the external data memory. Each data memory area includes on-chip peripheral area which consists of 64 words. When the external data memory area is accessed, instruction cycle can be 2 or more by wait function. 2.4.3 Data Memory Addressing There are following two types of data memory addressing. * Direct addressing The address is specified in the instruction field. * Indirect addressing The address is specified by the data pointer (DP). DP can get a bit reverse before addressing. It can update the DP value after accessing data memory.
19
PD77016
2.5 On-chip Peripheral Circuit The PD77016 includes serial interface, host interface, general input/output ports and wait cycle registers. They are mapped in both X and Y memory areas, and are accessed as memory mapped I/O by the PD77016 CPU. 2.5.1 Serial Interface Outline The PD77016 has 2 channel serial interfaces. Serial I/O clock must be provided from external. Frame length can be programmed independently to be 8 bits or 16 bits. MSB first or LSB first can also be selected. Data is input/output by hand shaking for an external device, and by interrupts, polling or wait function in internal. 2.5.2 Host Interface Outline The PD77016 has 8 bits parallel ports as host interface to input/output data to and from host CPU and DMA controller. When an external device accesses host interface, HA0 and HA1 pins; which are host address input pins; specifies bit 15 to bit 8 and bit 7 to bit 0. The PD77016 includes 3 registers consisting of 16 bits, which are dedicated for input data, output data and status. The PD77016 has three types of interface method for internal and external data; interrupts, polling and wait function. 2.5.3 General Input/output Ports Outline General input/output ports consist of 4 bits. User can set each port as input or output. The PD77016 includes two registers. One is 4 bits register for input/output data, and the other is 16 bits for control. 2.5.4 Wait Cycle Register The wait cycle registers consist of 16 bits. It is used to set wait cycle number when external memory is accessed. 0, 1, 3, or 7 wait cycle can be set in every data area which is divided into 8, and in every X and Y memory area which is divided into 4. When data area is accessed, wait cycle can be also set by WAIT pin.
20
PD77016
3. INSTRUCTIONS
3.1 Outline All PD77016 instructions are one-word instructions, consisting of 32 bits. And they are executed in 30 ns (min.) per instruction. There are following 9 instruction types. (1) Trinomial instructions : specify the Acc operation. 3 of general registers are specified optionally as the operation object. (2) Dyadic operation instructions : specify the Acc, ALU or shifter operation. 2 of general registers are specified optionally as the operation object. Some instructions can specify a general register and immediate data. (3) Monadic operation instructions : specify operations by ALU. 1 general register is specified optionally as the operation object. (4) Load/store instructions : transfer 16 bits data from memory to general registers, from general registers to memory and between general registers. (5) Inter-register transfer instructions : transfer data between general register and other registers. (6) Immediate data set instructions : set immediate data at general registers or each registers of address operation unit. (7) Branch instructions : specify the direction of the program flow. (8) Hardware loop instructions : specify times of instruction repeating. (9) Control Instructions : specify the control program.
21
PD77016
3.2 Instruction Set and Operation An operation is written according to the rules for expressing. An expression of instructions having two or more descriptions can have only one selected. (a) Expressions and selectable registers Expression and selectable registers are shown as follows.
Expression ro, ro', ro" rl, rl' rh, rh' re reh dp dn dm dpx dpy dpx_mod dpy_mod dp_imm xxx R0 - R7 R0L - R7L R0H - R7H R0E - R7E R0EH - R7EH DP0 - DP7 DN0 - DN7 DMX, DMY DP0 - DP3 DP4 - DP7
Selectable registers
DPn, DPn++, DPn- -, DPn##, DPn%%, !DPn## (n = 0 - 3) DPn, DPn++, DPn- -, DPn##, DPn%%, !DPn## (n = 4 - 7) DPn##imm (n = 0 - 7) content of memory address xxx Example When the content of DP0 register is 1000, DP0 shows the content of memory address 1000.
22
PD77016
(b) Modifying data pointers Data pointers are modified after memory access. The results are valid immediately after instruction execution. It is impossible to modify without memory access.
Description DPn DPn++ DPn- - DPn##
Operation No operation: DPn value does not change. DPn DPn+1 DPn DPn-1 DPn DPn + DNn: Adds DN0-DN7 corresponding to DP0-DP7 Example DP0 DP0 + DN0 (n = 0 - 3) DPn = ((DPL + DNn ) mod (DMX + 1)) + DPH (n = 4 - 7) DPn = ((DPL + DNn ) mod (DMY + 1)) + DPH
DPn%%
!DPn##
Access memory after DPn value is bit-reversed After memory access, DPn DPn + DNn DPn DPn + imm
DPn##imm
(c) Concurrent processing instructions q shows concurrent processing instruction. Instruction names are shown in abbreviation. TRI DYAD TRANS IMM BR LOOP CTR : Trinomial : Dyadic : Inter-register transfer : Immediate data set : Branch : Hardware loop : Control
MONAD : Monadic
(d) State of Overflow flag (OV) The following marks show the PD77016 overflow flag state. : Not affected
Caution
: 1 is set when the result of operation is overflow. If overflow does not occur after operation, OV is not reset, and keeps the state before operation.
23
PD77016 INSTRUCTION SET
Concurrent Writing Processing Name Mnemonic Operation TRI. DYAD. MONAD. Load/ store TRANS. IMM. BR. LOOP. Flag CTL. OV
24
Multiply add Multiply sub Sign unsign Multiply add Trinomial Unsign unsign Multiply add
ro = ro + rhrh' ro = ro-rhrh' ro = ro + rhrl (rl should be a plus integral number.) ro=ro+rlrl' (rl and rl' should be a plus integral number.) ro=(ro>>1)+rhrh' ro = (ro>>16)+rhrh' ro=rhrh' ro"=ro+ro' ro'=ro+imm ro"=ro-ro' ro'=ro-imm ro'=ro SRA rl ro'=ro SRA imm
ro ro+rhrh' ro ro-rhrh' ro ro+rhrl

ro ro+rlrl'
1 bit shift Multiply add 16 bits shift Multiply add Multiply Add Immediate add Sub Immediate sub Arithmetic right shift Immediate arithmetic right shift Logic right shift Immediate Logic right shift Logic left shift Immediate logic left shift
ro ro +rhrh' 2 ro ro 16 +rhrh' 2 ro rhrh' ro" ro+ro' ro' ro+imm (imm 1) ro" ro-ro' ro' ro-imm (imm 1) ro' ro >> rl ro' ro >> imm

Dyadic
ro'=ro SRL rl ro'=ro SRL imm ro'=ro SLL rl ro'=ro SLL imm
ro' ro >> rl ro' ro >> imm ro' ro << rl ro' ro << imm
PD77016
Concurrent Writing Processing Name Mnemonic ro" ro & ro' ro' ro & imm ro" ro | ro' ro' ro | imm ro" ro ^ ro' ro ro ^ imm if(ro0x007FFFFFFF) {ro' 0x007FFFFFFF] else if, (ro<0xFF80000000) {ro' 0xFF80000000} else {ro' ro} if (ro>0x007FFF0000) {ro' 0x007FFF0000} else if, (ro>0xFF80000000) {ro' 0xFF80000000} else {ro' (ro + 0x8000) & 0xFFFFFF0000} ro' log2 ro' ro ( 1 ) ro Operation TRI. DYAD. MONAD. Load/ store TRANS. IMM. BR. LOOP.
Flag CTL. OV
And Immediate and Or Immediate or Dyadic Exclusive or Immediate exclusive or Less than
ro" = ro & ro' ro' = ro & imm ro" = ro | ro' ro' = ro | imm ro" = ro ^ ro' ro = ro ^ imm ro" = LT(ro, ro')
Clear Increment Decrement Absolute
CLR(ro) ro' = ro + 1 ro' = ro - 1 ro' = ABS (ro)

One's complement Two's complement Monadic Clip
ro' = ~ro ro' = -ro ro' = CLIP (ro)

Round
ro' = ROUND (ro)
PD77016
Exponent Substitution
ro' = EXP (ro) ro' = ro
25
26
Name Mnemonic Operation TRI. Cumulation Degression Monadic Division ro'+ = ro ro'- = ro ro'/ = ro ro' ro'+ro ro' ro'-ro if (sign(ro')==sign(ro)) {ro' (ro'-ro)<<1} else {ro' (ro'+ro)<<1} if (sign(ro')==0 {ro' ro'+1} ro dpx, ro' dpy ro dpx, dpy rh dpx rh, ro dpy dpx rh, dpy rh' dest dpx, dest' dpy dest dpx, dpy source dpx source, dest dpy dpx source, dpy source' Parallel load/store Note1, Note2. ro=dpx_mod ro'=dpy_mod ro=dpx_mod dpy_mod=rh dpx_mod=rh ro=dpy_mod dpx_mod=rh dpy_mod=rh' Load/store Section load/store Note1, Note2, Note 3. dest=dpx_mod dest'=dpy_mod dest=dpx_mod dpy_mod=source dpx_mod=source dest=dpy_mod dpx_mod=source dpy_mod=source'
Concurrent Writing Processing DYAD. MONAD. Load/ store TRANS. IMM. BR. LOOP.
Flag CTL. OV

Note 1. 2. 3.
One or both of a mnemonic pair can be written. After execution of load/store, data is modified by mod. One of following mnemonic should be selected: dest, dest' = {ro, reh, re, rh, rl}, source, source' = {re, rh, rl}.
PD77016
Concurrent Writing Processing Name Mnemonic Operation TRI. DYAD. MONAD. Load/ store TRANS. IMM. BR. LOOP.
Flag CTL. OV
Direct addressing load/store Note 1. Load/store Immediate index load/store Note 2.
dest = addr addr = source dest = dp_imm dp_imm = source
dest addr addr source dest dp dp source dest rl rl source rl imm
Inter-register transfer
Inter-register transfer Note 3.
dest = rl rl = source
Immediate data set
rl = imm (provided imm = 0-0xFFFF) dp = imm (provided imm = 0-0xFFFF) dn = imm (provided imm = 0-0xFFFF) dm = imm (provided imm = 1-0xFFFF)
dp imm
Immediate data set
dn imm
dm imm
Note 1. 2. 3.
One of following mnemonic should be selected: dest = {ro, reh, re, rh, rl}, source = {re, rh, rl}, add = One of following mnemonic should be selected: dest = {ro, reh, re, rh, rl}, source = {re, rh, rl}. Any register except general registers should be selected as dest or source.
0: X-0xFFFF:X memory 0: Y-0xFFFF:Y memory
.
PD77016
27
28
Name Mnemonic Operation TRI. Jump Inter-register indirect jump Subroutine call JMP imm JMP dp CALL imm PC imm PC dp SP SP + 1 STK PC + PC imm SP SP + 1 STK PC + 1 PC dp PC STK SP SP - 1 PC STK STK SP - 1 Restore the interrupt enable flag start repeat end RC count RF 0 PC PC RC RC - 1 PC PC + 1 RF 1 RC count RF 0 PC PC RC RC - 1 PC PC + 1 RF 1 Branch Inter-register indirect subroutine call CALL dp Return RET Return from interrupt RETI Repeat REP count Loop Hardware loop LOOP count (Mnemonics more than two lines) start repeat end Loop pop LPOP LC LSR3 LE LSR2 LS LSR1 LSP LSP-1 PC PC + 1 CPU stop Conditional judge Control No operation Halt If Forget interrupt NOP HALT IF (ro cond) FINT Forget interrupt request
Concurrent Writing Processing DYAD. MONAD. Load/ store TRANS. IMM. BR. LOOP.
Flag CTL. OV
PD77016
PD77016
4. ELECTRICAL SPECIFICATIONS
Absolute maximum ratings (TA = +25 C)
Parameters Power supply voltage Input voltage Output voltage Storage temperature Operating ambient temperature Symbol VDD VI VO Tstg TA Conditions Ratings -0.5 to +7.0 -0.5 to VDD + 0.5 -0.5 to VDD + 0.5 -65 to +150 -40 to +85 Unit V V V C C
Caution
Exposure to Absolute Maximum Ratings for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The parameters apply independently. The device should be operated within the limits specified under DC and AC Characteristics.
Capacitance (TA = +25 C, VDD = 0 V)
Parameters Input capacitance Output capacitance Symbol CI CO Conditions fc = 1 MHz Unmeasured pins returned to 0 V. MIN. TYP. MAX. 15 15 Unit pF pF
DC characteristics (TA=-40 to +85 C, VDD = 5 V 10 %)
Parameters High level input voltage Symbol VIH Conditions except for RESET, CLKIN, INT1 - INT4, WAIT, HCS, HRD, HWR, TCK, TDI, TMS RESET, INT1 - INT4, WAIT, HCS, HRD, HWR, TCK, TDI, TMS except for RESET, CLKIN, INT1 - INT4, WAIT, HCS, HRD, HWR, TCK, TDI, TMS RESET, INT1 - INT4, WAIT, HCS, HRD, HWR, TCK, TDI, TMS MIN. 2.2 TYP. MAX. VDD + 0.5 Unit V
VIHC
0.7VDD
VDD + 0.5
V
Low level input voltage
VIL
-0.5
+0.8
V
VILC
-0.5
0.2VDD
V
High level CLKIN voltage Low level CLKIN voltage High level output voltage Low level output voltage Low level input current High level input leak current Low level input leak current Power supply current
VIHX VILX VOH VOL IIL ILIH ILIL IDD Note IOH = -2.5 mA IOL = 2.5 mA TDI, TMS, VI = 0 V VI = VDD except for TDI, TMS, VI = 0 V Active mode, tcCI = 15 ns VIH = VDD, VIL = 0 V, no load HALT mode, tcCI = 15 ns, VIH = VDD, VIL = 0 V, no load CLKIN = 0 V VIH = VDD, VIL = 0 V, no load
0.8VDD -0.5 0.8VDD
VDD + 0.5 0.2VDD
V V V
0.4 -400 10 -10 140 300
V
A A A
mA
IDDH
80 10
mA
IDDS
A
Note
The TYP. value is measured when a general program is executed, and VDD = 5 V conditon. The MAX. value is measured when a special program that max. switching required is executed, and VDD = 5.5 V condition.
29
PD77016
Measurement Standards Common to Switching Characteristics
0.8 VDD 0.5 VDD 0.2 VDD 0.8 VDD 0.5 VDD 0.2 VDD
CLKIN
Test points
Input (except for CLKIN)
2.2 V 1.5 V 0.8 V
Test points
2.2 V 1.5 V 0.8 V
Output
2.2 V 1.5 V 0.8 V
Test points
2.2 V 1.5 V 0.8 V
AC Characteristics (TA = -40 to +85 C, VDD = 5 V 10%, CL = 30 pF)
Clock
Required Timing Condition
Parameters CLKIN cycle time CLKIN high level width CLKIN low level width CLKIN rise/fall time Symbol tcCI twCIH twCIL trfCI Conditions MIN. 15 6.75 6.75 TYP. MAX. 500 0.55 tcCI 0.55 tcCI 6 Unit ns ns ns ns
Switching Characteristics
Parameters CLKOUT cycle time CLKOUT level width CLKOUT rise/fall time Symbol tcCO twCO trfCO tcCI - 3 3 Conditions MIN. TYP. 2tcCI MAX. Unit ns ns ns
30
PD77016
Reset, Interrupt
Required Timing Condition
Parameters RESET low level width RESET recovery time INT1-INT4 low level width INT1-INT4 recovery time Symbol tw(RL) trec(R) tw(INTL) trec(INT) Conditions MIN. 4tcCO 4tcCO 3tcCO 3tcCO TYP. MAX. Unit ns ns ns ns
Clock Input/Output Timing
tcCI trfCI twCIH CLKIN twCIL trfCI
tcCO twCO CLKOUT twCO trfCO trfCO
Reset, Interrupt Timing
tw(RL) RESET trec(R)
Interrupt Timing
trec(INT) tw(INTL) INT1 - INT4
31
PD77016
External Data Memory Access
Required Timing Condition
Parameters Read data setup time Read data hold time WAIT setup time WAIT hold time Symbol tsuDDRD thDDRD tsuWA thWA Conditions MIN. 14 0 8 0 TYP. MAX. Unit ns ns ns ns
Switching Characteristics
Parameters Address output delay time MRD output delay time MRD hold time Write data setup time Symbol tdDA tdDR thDR tsDDWD Conditions MIN. 0 0 0 tcCI + twCIH - 15 + tcDWNote 0 twCIH - 4 twCIL - 4 tcCI - 4 + tcDWNote tcCI - 4 15 TYP. MAX. 6 8 8 Unit ns ns ns ns
Write data output hold time MWR output delay time MWR setup time MWR low level width
thDDWD tdDW tsuDW twDWL
ns ns ns ns
MWR high level width
twDWH
ns
Note tcDW: Data wait cycle
32
PD77016
External Data Memory Read Operation
CLKOUT
tdDA DA0 DA15, X/Y
tsuDDRD
thDDRD
D0 - D15
tdDR MRD
thDR
tsuWA
thWA
tsuWA
thWA
WAIT
External Data Memory Write Operation
CLKOUT
tdDA
DA0 - DA15, X/Y
tsDDWD Hi-Z
thDDWD Hi-Z
D0 - D15
tdDW twDWL MWR
tsuDW twDWH
tsuWA
thWA
tsuWA
thWA
WAIT
33
PD77016
External Instruction Memory Access Required Timing Condition
Parameters ID setup time (to CLKOUT ) ID hold time (to CLKOUT ) Symbol tsuID thID Conditions MIN. 14 0 TYP. MAX. Unit ns ns
Switching Characteristics
Parameters IA output delay time IA hold time ID write setup time ID write hold time PWR output delay time Address PWR setup time PWR setup time PWR width Symbol tdIA thIA tsIDW thIDW tdIW td(IAV-IWV) tsuIW twIW tcCI + twCIH -4 twCIL - 4 tcCO - 4 + tcIW 0 tcCI + twCIH - 15 0 10 Conditions MIN. TYP. 10 6 MAX. Unit ns ns ns ns ns ns ns ns
Remark tcIW: Instruction wait cycle
34
PD77016
External Instruction Memory Read Operation
CLKOUT
thIA tdIA IA0 - IA15 Hi-Z
tsuID
thID
ID0 - ID31
tdIW
PWR
Hi-Z
RESET
External Instruction Memory Write Operation
CLKOUT
thIA
IA0 - IA15
thIDW tsIDW Hi-Z Hi-Z
ID0 - ID31
td(IAV-IWV) twIW PWR
tsuIW
35
PD77016
Bus Arbitration
Required Timing Condition
Parameters HOLDRQ setup time HOLDRQ hold time Symbol tsuHRQ thHRQ Conditions MIN. 8 0 TYP. MAX. Unit ns ns
Switching Characteristics
Parameters BSTB hold time BSTB output delay time HOLDAK output delay time HOLDAK hold time Data hold time when bus arbitration Data valid time after bus arbitration Symbol thBS tdBS tdHAK thHAK th(BS-D) tv(BS-D) Conditions MIN. 0 0 0 0 TYP. MAX. 6 6 6 6 15 15 Unit ns ns ns ns ns ns
36
Bus Arbitration Timing (Bus idle)
CLKOUT
(Bus busy)
Bus idle
Bus release
Bus idle
(Bus busy)
thBS
tdBS
BSTB tsuHRQ HOLDRQ tdHAK thHAK thHRQ tsuHRQ thHRQ
HOLDAK th(BS-D) X/Y, DA0 - DA15, MRD, MWR Hi-Z tv(BS-D)
PD77016
37
38
Bus Arbitration Timing (Bus busy)
CLKOUT
(Bus busy)
Bus busy
Bus idle
Bus release
Bus idle
(Bus busy)
thBS
tdBS
BSTB tsuHRQ thHRQ HOLDRQ thHAK tsuHRQ thHRQ
tdHAK HOLDAK th(BS-D) X/Y, DA0 - DA15, MRD, MWR Hi-Z
tv(BS-D)
PD77016
Bus Arbitration Timing (Bus slave)
CLKOUT
Load/store External Memory
Bus idle
Bus hold
Bus idle
BSTB
HOLDRQ
X/Y, DA0 - DA15, MRD, MWR
Hi-Z
Hi-Z
HOLDAK
PD77016
39
PD77016
Serial Interface Required Timing Condition
Parameters SCK input cycle time SCK input high/low level width SCK input rise/fall time SOEN recovery time SOEN hold time SIEN recovery time SIEN hold time SI setup time SI hold time Symbol tcSC twSC trfSC trecSOE thSOE trecSIE thSIE tsuSI thSI 10 5 10 5 10 0 Conditions MIN. 2tcCO 25 3 20 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns
Switching Characteristics
Parameters SORQ output delay time SORQ hold time SO valid time SO hold time SIAK output delay time SIAK hold time Symbol tdSOR thSOR tvSO thSO tdSIA thSIA 0 0 Conditions MIN. 0 0 0 TYP. MAX. 30 30 30 60 30 30 Unit ns ns ns ns ns ns
Notes for Serial Clock Serial clock inputs SCK1 and SCK2 are sensitive to any kind of interfering signals (noise on power supply, induced voltage, etc.). Spurious signals can cause malfunction of the device. Special care for the serial clock design should be taken. Careful grounding, decoupling and short wiring of SCK1 and SCK2 are recommended. Intersection of SCK1 and SCK2 with other serial interface lines or close wiring to lines carrying high frequency signals or large changing currents should be avoided. It considers for the serial clock to make a waveform stable especially about the rising and falling.
Example 1. good example Straight rising form and falling form
Example 2. no good example It doesn't bound. It doesn't make noise one above another.
Example 3. no good example It doesn't make a stair stepping.
40
Serial Output Timing 1
tcSC twSC SCK1, SCK2 tdSOR thSOR twSC
trfSC
trfSC
SORQ1, SORQ2 trecSOE trecSOE thSOE thSOE SOEN1, SOEN2
tvSO
tvSO
thSO
SO1, SO2
Hi-Z
1st
Last
Hi-Z
PD77016
41
42
Serial Output Timing 2 (Continual output)
tcSC twSC SCK1, SCK2 tdSOR thSOR twSC
trfSC
trfSC
SORQ1, SORQ2 trecSOE thSOE
SOEN1, SOEN2
tvSO Hi-Z
SO1, SO2
Last
1st
Last
PD77016
Serial Input Timing 1
tcSC twSC SCK1, SCK2 tdSIA thSIA twSC
trfSC
trfSC
SIAK1, SIAK2 trecSIE trecSIE thSIE thSIE
SIEN1, SIEN2
tsuSI
thSI
SI1, SI2
1st
2nd
3rd
PD77016
43
44
Serial Input Timing 2 (Continual input)
tcSC twSC SCK1, SCK2 tdSIA thSIA twSC
trfSC
trfSC
SIAK1, SIAK2 trecSIE thSIE SIEN1, SIEN2
tsuSI
thSI
SI1, SI2
Last-1
Last
1st
2nd
3rd
PD77016
PD77016
Host Interface Required Timing Condition
Parameters HRD delay time HRD width HCS, HA0, HA1 read hold time HCS, HA0, HA1 write hold time HRD, HWR recovery time HWR delay time HWR width HWR hold time HWR setup time Symbol tdHR twHR thHCAR thHCAW trecHS tdHW twHW thHDW tsuHDW Conditions MIN. 0 2tcCO 5 5 2tcCO 0 2tcCO 5 20 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns
Switching Characteristics
Parameters HRE, HWE output delay time HRE, HWE hold time HRD valid time HRD hold time Symbol tdHE thHE tvHDR thHDR 0 Conditions MIN. TYP. MAX. 30 20 30 Unit ns ns ns ns
45
46
Host Read Interface Timing
CLKOUT
HCS, HA0, HA1
thHCAR tdHR twHR trecHS
HRD
thHDR
tvHDR HD0 - HD7 Hi-Z Hi-Z
tdHE
thHE
HRE
PD77016
Host Write Interface Timing
CLKOUT
HCS, HA0, HA1
thHCAW tdHW
twHW
trecHS
HWR thHDW tsuHDW
HD0 - HD7
tdHE thHE
HWE
PD77016
47
PD77016
General Input/Output Ports Required Timing Condition
Parameters Port input setup time Port input hold time Symbol tsuPI thPI Conditions MIN. 10 10 TYP. MAX. Unit ns ns
Switching Characteristics
Parameters Port output delay time Symbol tdPO Conditions MIN. 0 TYP. MAX. 30 Unit ns
General Input/Output Ports Timing
CLKOUT
tdPO P0 - P3 (Output) tsuPI thPI P0 - P3 (Input)
48
PD77016
Debugging Interface (JTAG)
Required Timing Condition
Parameters TCK cycle time TCK high level width TCK low level width TCK rise/fall time TMS, TDI setup time TMS, TDI hold time Input pin setup time Input pin hold time Symbol tcTCK twTCKH twTCKL trfTCK tsuDI thDI tsuJIN thJIN 10 15 10 0 Conditions MIN. 4tcCO 50 50 3 20 TYP. MAX. Unit ns ns ns ns ns ns ns ns
Switching Characteristics
Parameters TDO output delay time Output pin output delay time Symbol tdDO tdJOUT Conditions MIN. 0 TYP. MAX. 30 30 Unit ns ns
Debugging Interface Timing
tcTCK twTCKH twTCKL trfTCK trfTCK
TCK
tsuDI TMS, TDI
thDI
Valid
Valid
Valid
tdDO
TDO
tsuJIN
thJIN
Capture state
Valid
tdJOUT
Update state
Remark For the details of JTAG, refer to "IEEE1149.1."
49
PD77016
5. PACKAGE DRAWING
160 PIN PLASTIC QFP (FINE PITCH) (
24)
A B 120 121 81 80
detail of lead end
C
D
S Q R
F G
160 1 H I
M
41 40 J K
P N
NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition.
M L
ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 26.00.2 24.00.2 24.00.2 26.00.2 2.25 2.25 0.22 +0.05 -0.04 0.10 0.5 (T.P.) 1.00.2 0.50.2 0.17 +0.03 -0.07 0.10 2.7 0.40.1 3 +7 -3 INCHES 1.024+0.008 -0.009 0.9450.008 0.9450.008 1.024+0.008 -0.009 0.089 0.089 0.0090.002 0.004 0.020 (T.P.) 0.039+0.009 -0.008 0.020 +0.008 -0.009 0.007 +0.001 -0.003 0.004 0.106 0.016 +0.004 -0.005 3 +7 -3
3.3 MAX. 0.130 MAX. S160GM-50-JMD,KMD
50
PD77016
6. RECOMMENDED SOLDERING CONDITIONS
When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. For more details, refer to our document "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (C10535E). Surface mount device
PD77016GM-KMD: 160-pin plastic QFP (FINE PITCH) (24 x 24 mm)
Process Infrared ray reflow Conditions Peak temperature: 235 C or below (Package surface temperature), Reflow time: 30 seconds or less (at 210 C or higher), Maximum number of reflow processes: 1 time, Exposure limitNote : 7 days (20 hours pre-baking is required at 125 C afterwards). VPS Peak temperature: 215 C or below (Package surface temperature), Reflow time: 40 seconds or less (at 200 C or higher), Maximum number of reflow processes: 1 time, Exposure limitNote : 7 days (20 hours pre-baking is required at 125 C afterwards). Partial heating method Pin temperature: 300 C or below, Heat time: 3 seconds or less (Per each side of the device). - VP15-207-1 Symbol IR35-207-1
Note Maximum allowable time from taking the soldering package out of dry pack to soldering. Storage conditions: 25 C and relative humidity of 65 % or less. Caution Apply only one kind of soldering condition to a device, except for "partial heating method", or the device will be damaged by heat stress.
51
PD77016
[MEMO]
52
PD77016
[MEMO]
53
PD77016
[MEMO]
54
PD77016
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
55
PD77016
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96.5
2

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